Integrated circuit devices such as transistors are typically formed on the surfaces of semiconductor substrates. Metal layers are formed over the integrated circuit devices, and are used to interconnect the integrated circuit devices as functional circuits. There may be as many as ten metal layers formed over a semiconductor substrate.
Since the resistance of a metal line is related to its size, and a lower resistance leads to better performance of the respective integrated circuits, it is preferred that the metal lines are thick, wide, and short in order to have a small resistance. However, the requirement of forming thick and wide metal lines conflicts with the requirement of reducing chip area usage. Accordingly, metal layers typically adopt hierarchical structures, wherein upper metal layers have the thicknesses and widths equal to or greater than the thicknesses and widths, respectively, of lower metal layers. This is because the lower metal layers have more metal lines, and hence have to be narrow to incorporate the large amount of metal lines. The upper metal layers are relatively small in number, and can be larger in size.
When the integrated circuit manufacturing process advances to 20 nm technology or smaller, the pitch of the metal lines, particularly in the lower metal layers, are close to the wavelength of the yellow light, wherein the yellow light is used for exposing photoresists that are used for defining the patterns of metal layer. Special techniques need to be used to reduce or eliminate the problem caused by the small pitch of the metal lines. For example, two photoresists and two etching processes may be needed for defining the pattern of one metal layer. This, however, results in the increase in the manufacturing cost and the reduction in the yield.